The present application relates to a gallium nitride-based semiconductor element, an optical device using the same, and an image display apparatus using the optical device.
A light-emitting element (GaN-based semiconductor light-emitting element) including an active layer composed of a gallium nitride (GaN) compound semiconductor can realize a wide light-emission wavelength range from ultraviolet to infrared by controlling bandgap energy using a mixed crystal composition and/or the thickness of the active layer. GaN-based semiconductor light-emitting elements which emit various colors have already been commercially available and have been used in various applications, such as an image display apparatus, a lighting device, a light source for an inspection device, a light source for a disinfection device, and a light source for a medical inspection device. In addition, a semiconductor laser and a light-emitting diode (LED), which emit violet color, have also been developed and have already been used as a pickup for writing and reading data on a large capacity optical disc.
In general, a GaN-based semiconductor light-emitting element has a structure including a first GaN-based compound semiconductor layer having an n-type conductivity, an active layer, and a second GaN-based compound semiconductor layer having a p-type conductivity laminated in that order on a substrate.
Hereinafter, a GaN-based semiconductor light-emitting element of a related art will be described.
The following has been disclosed by S. Keller et al., “Effect of the growth rate and the barrier doping on the morphology and the properties of InGaN/GaN quantum wells,” J. Cryst. Growth. 195, (1998), pp. 258 to 264 (3.2 Effect of the silicon doping during LT GaN˜) (hereinafter referred to as “Non-Patent Document 1).
A Si doping concentration of a GaN barrier was changed from 0 to 3×1019/cm3. In addition to a slight decrease in superlattice period concomitant with an increase in Si doping concentration of the barrier, by a high resolution x-ray diffraction analysis, a significant decrease in full-width at half maximum was confirmed for both a first-order and a second-order superlattice peak. That is, by increasing the Si doping concentration of a multi-quantum well from 0 to 3×1019/cm3, the full-width at half maximum of the first-order superlattice peak was decreased from 312 to 212 arcsec, and the full-width at half maximum of the second-order superlattice peak was decreased from 589 to 234 arcsec.
By H. Kim et al., “Electromigration-induced failure of GaN multi-quantum well light emitting diode,” Electronics Letters, Vol. 36, No. 10 (2000), pp 908 to 910 (summary) (hereinafter referred to as “Non-Patent Document 2), it has been disclosed that the life of a GaN multi-quantum well (MQW) LED can be extrapolated by using an electromigration-induced failure model.
In Japanese Unexamined Patent Application Publication No. 2001-203386 (paragraphs 0008 and 0018, and FIG. 6) (hereinafter referred to as “Patent Document 1”) titled “III-nitride light-emitting device enhancing light generation ability”, the following has been disclosed.
The invention of the Patent Document 1 relates to an inversion type III-nitride light-emitting device (LED) having a high light generation ability as a whole. The device of a large area (>400×400 μm2) has at least one n electrode, and the n electrode is provided to surround metallization of a p electrode, so that a series resistance is decreased. The metallization of the p electrode is opaque and has a high reflectivity, ohmic properties, and superior current diffusivity. In order to obtain an electrical and a thermal connection between an LED chip and a package, an intermediate material, that is, a lower mount, can be used. This device can include a superstrate structure having a high refractive index (n>1.8) so as to improve a light-extraction efficiency.
According to Patent Document 1, by decreasing a thermal resistance from a pn junction to a lightning package while a light-extraction amount is increased, a high output LED is provided which has a large area, such as more than 400×400 μm2, and a significantly high light generation ability. According to the invention of the Patent Document 1, in order to realize the above LED, an inversion structure including an opaque p electrode having a low resistance and a high reflectance is used.
The following technique has been disclosed in Japanese Unexamined Patent Application Publication No. 2001-237458 (paragraphs 0009 and 0029, and FIG. 6) (hereinafter referred to as “Patent Document 2”) titled “Method for manufacturing group III nitride LED having enhanced light-emission ability”.
The invention of the Patent Document 2 relates to an inversion type group III nitride light-emitting device (LED) having an enhanced entire light-emission ability. This device of a large area (>400×400 μm2) has at least one n electrode surrounded by a p electrode metal cover so as to obtain a low series resistance. The p electrode metal cover is opaque and has a high reflectance, ohmic properties, and superior current diffusivity. An intermediate material or a lower mount may be used to prepare an electrical and a thermal connection between the LED and a package. This device may include an upper-layer substrate having a high refractive index (n>1.8) which can obtain a further improvement in light-extraction efficiency.
According to Patent Document 2, since a thermal resistance from a pn junction to a lamp package is decreased while light extraction is enhanced, a high power LED having a maximum light-emission ability and a large area, such as more than 400×400 μm2, can be provided. In order to realize this LED, the invention of the Patent Document 2 uses an inversion structure incorporating an opaque p electrode having a low resistance and a high reflectance.
In Japanese Unexamined Patent Application Publication No. 2002-299685 (paragraphs 0004, 0009 and 0010, and 0031, and FIGS. 1 and 3) (hereinafter referred to as “Patent Document 3”) titled “Indium gallium nitride smooth structure for group III nitride device”, the following technique has been disclosed.
According to Patent Document 3, an inclined smooth region containing indium, which is prepared for growth in an active region, is formed between a substrate and an active region of a group III nitride light-emitting device. In one embodiment of this invention, the inclined smooth region has an inclined composition. In another embodiment, the inclined smooth region has an inclined dopant concentration. In several embodiments, the inclined smooth region is separated from the active region by a spacer layer having a constant composition and dopant concentration. The inclined smooth region of the invention according to the Patent Document 3 can improve surface properties of a layer grown on the inclined smooth region, in particular, on the active region.
In Patent Document 3, a smooth layer is highly doped as compared to the spacer layer. The smooth layer is doped with Si at a concentration, for example, in the range of 2×1017 to 2×1019/cm3. In the first embodiment, the spacer layer is an n-type layer doped with Si at a concentration, for example, in the range of 0 to 2×1018/cm3.
The spacer layer of the first embodiment has a lower dopant concentration than that of an n-type region 12; hence, the spacer layer is a layer having a higher resistance, which can help current to uniformly spread in the active region and can prevent the current from concentrating at a shortest path between an n contact and a p contact. The thickness of the spacer layer is selected in accordance with the dopant concentration thereof so that the spacer layer does not remarkably increase a forward voltage of the device.
According to Patent Document 3, the indium-containing smooth structure has several advantages. First of all, by using the smooth structure, even after undesired three-dimensional growth in an island shape starts, a two-dimensional step-flow type growth on a smooth semiconductor surface can be recovered. The three-dimensional growth in an island shape may be induced by large misalignment of a substrate surface or an insufficient surface treatment, or may be induced at a growth initiation step, which is designed to decrease a crystalline dislocation density, such as silicon implantation. As described above, the surface condition has influence on the device properties, and the smooth structure can improve both efficiency and reliability of a group III nitride LED.
In Japanese Unexamined Patent Application Publication No. 2002-319702 (paragraphs 0016 and 0017) (hereinafter referred to as “Patent Document 4”) titled “Method for manufacturing nitride semiconductor element and nitride semiconductor element”, the following technique has been disclosed.
The nitride semiconductor element of Patent Document 4 has a first nitride semiconductor layer, an active layer laminated thereon, and a second nitride semiconductor layer laminated on the active layer and having an opposite conductivity to that of the first nitride semiconductor layer, in which a growth temperature of the second nitride semiconductor layer is set to 900° C. or less, and the second nitride semiconductor has a thickness forming a smooth surface.
When the nitride semiconductor layer is a gallium nitride layer, although a gallium nitride layer grown at approximately 950° C. is generally liable to form growth pits, when it is grown at a lower temperature of 900° C. or less, since a surface diffusion length of a group III element is decreased, a flat film having a small number of growth pits can be obtained. As a result, when a device is formed, for example, a decrease in leakage current can be realized.
In Japanese Unexamined Patent Application Publication No. 2003-59938 (paragraphs 0062 to 0067, and FIG. 14) (hereinafter referred to as “Patent Document 5”) titled “Nitride semiconductor laminate and semiconductor element thereof”, the following technique has been disclosed.
FIG. 13 is a view illustrating an LED element of a related art and corresponds to FIG. 14 of the Patent Document 5.
Example 3 of the Patent Document 5 will be described in which Patent Document 5 is applied to a light-emitting diode (LED) formed of a nitride semiconductor. FIG. 13 is a view showing the structure of an LED to which the invention of the Patent Document 5 is applied, in which reference numeral 241 indicates a SiC substrate, 242 indicates an AlN buffer layer (100 nm), 243 indicates a Si-doped GaN layer (1 μm), 244 indicates an InGaN graded layer (30 nm), 245 indicates an undoped InGaN/GaN superlattice (active layer), 246 indicates an InGaN graded layer (30 nm), 247 indicates an Mg-doped GaN layer (500 nm), 248 indicates an Al/Au electrode, and 249 indicates a Pd/Au electrode.
In a manner similar to that of Example 1, after an epitaxial structure was formed on the SiC substrate 241 by a metal-organic vapor phase epitaxial (MOVPE) method, etching was performed by an electron cyclotron resonance (ECR) etching method, and electrodes were then formed by electron beam deposition. The active layer 245 was an InGaN/GaN superlattice, the In composition of a barrier layer of this superlattice was 6%, and the In composition of a well layer was 10%. The thickness of the barrier layer and that of the well layer were 5 nm and 2 nm, respectively, and the number of the well layers was 5. The In composition of the InGaN layer 244 inserted between the n-type impurity layer 243 and the active layer 245 was increased from 0% to 6% from the n-type impurity layer 243 to the active layer 245. By the structure described above, the bandgap was gradually decreased from the substrate side to the surface side.
In addition, the In composition of the InGaN layer 246 inserted between the active layer 245 and the p-type impurity layer 247 was decreased from 6% to 0% from the active layer 245 to the p-type impurity layer 247. By the structure described above, the bandgap was gradually increased from the substrate side to the surface side. The thicknesses of the two InGaN graded layers 244 and 246 were fixed to 30 nm. In addition, for the InGaN graded layer 244 inserted between the n-type impurity layer 243 and the active layer 245, a structure in which no Si impurity, which is an n-type impurity, was doped and a structure in which a Si impurity at a concentration of 1×1018/cm3 was doped were formed.
In addition, for the InGaN graded layer 246 inserted between the active layer 245 and the p-type impurity layer 247, a structure in which no Mg impurity, which is a p-type impurity, was doped and a structure in which an Mg impurity at a concentration of 1×1018/cm3 was doped were formed.
By applying a voltage to these two structures, each LED is driven to emit light. By using the invention of the Patent Document 5, when an n-type or a p-type impurity at a concentration of 1×1018/cm3 was doped in the InGaN graded layer 244 or 246, the light-emission output could be increased even at a low voltage. Furthermore, when both doping of an n-type impurity (Si) and a p-type impurity (Mg) are performed, light emission can be performed at a low voltage of 3V or less.
In Japanese Unexamined Patent Application Publication No. 2004-112002 (paragraphs 0011 and 0012, and FIG. 1) (hereinafter referred to as “Patent Document 6”) titled “Nitride semiconductor element”, the following technique has been disclosed.
FIG. 14 is a view illustrating a GaN semiconductor element (LED element) of a related art and corresponds to FIG. 1 of the Patent Document 6.
FIG. 14 is a schematic cross-sectional view showing the structure of a nitride semiconductor element (LED element) of one embodiment of the invention according to the Patent Document 6. The nitride semiconductor element of this embodiment is formed of (1) a buffer layer 102 of AlGaN, (2) an undoped GaN layer 103, (3) an n-type contact layer 104 of Si-doped GaN, (4) an undoped GaN layer 105, (5) a Si-doped GaN layer 106, (6) an undoped GaN layer 107, (7) a GaN/InGaN superlattice n-type layer 108, (8) an active layer 109 having a multi-quantum well structure in which InGaN layers and GaN layers are provided as a well layer and a barrier layer, respectively, (9) a p-AlGaN/p-InGaN superlattice p-type layer 110, and (10) an Mg-doped GaN/Si-doped GaN modulated doped p-side contact layer 111 provided in that order on a sapphire substrate 101, and in addition, a p-side and an n-side electrode are formed as described below.
For example, after a corner of the element from the p-side contact layer 111 to the undoped GaN layer 105 is removed by etching so as to expose part of the n-contact layer 104, an n-ohmic electrode 121 is formed on the exposed part of the n-type contact layer 104.
In addition, as the p-side electrode, after a p-ohmic electrode 122 is formed almost all over the p-side contact layer 111, a p-pad electrode 123 is formed on part of the p-ohmic electrode 122.
The nitride semiconductor element of this embodiment is particularly characterized in that the p-side contact layer 111 is formed of a modulated doped layer obtained by alternately laminating an Mg-doped GaN layer 111a and a Si-doped GaN layer 111b; hence, a leakage current is decreased, and an electrostatic withstand voltage is improved.
In this embodiment, a preferable Si doping concentration of the p-side contact layer 111 (Si-doped GaN layer 111b) is set in the range of 1×1017 to 1×1021/cm3, and more preferably in the range of 1×1018 to 5×1019/cm3. The reasons for this are that when the concentration is 1×1017/cm3 or more, a significant effect of decreasing a leakage current can be obtained, and when the concentration is more than 1×1021/cm3, the crystallinity is degraded, and the light-emission efficiency is liable to be degraded.
By X. A. Cao et al., “Microstructure origin of leakage current InGaN/InGaN light-emitting diodes,” J. Cryst. Growth. 264, (2004), pp. 172 to 177 (3. Results and discussion, FIGS. 2(a) and 2(b)) (hereinafter referred to as “Non-Patent Document 3), typical reverse I-V characteristics of LED when the temperature is increased (FIG. 2(a)) and a proportional relationship of leakage current to an active layer area function area) (FIG. 2(b)) have been disclosed. In addition, according to the Non-patent Document 3, it is confirmed that a relationship of topography to a current image corresponds to a relationship of V-defects with associated mixed dislocation or screw dislocation to a highly localized junction leakage current at a low bias application.
By T. Akasaka et al., “High luminescent efficiency of InGaN multiple quantum wells grown on InGaN underlying layers,” App. Phys. Lett. Vol. 85, No. 15 (2004), pp 3089 to 3091 (lines 29 to 36 of the left column of page 3089, and line 19 of the right column of page 3089 to line 1 of the left column of page 3090) (hereinafter referred to as “Non-Patent Document 4), the following technique has been disclosed.
By an InGaN underlayer having a thickness of approximately 50 nm, the number of nonradiative recombination centers of an InGaN multi-quantum well was significantly decreased, and as a result, although the internal quantum efficiency (ηint) of photoluminescence (PL) at room temperature, which has been reported, was approximately 0.3, a sufficiently high internal quantum efficiency (ηint) of 0.71 was obtained by the InGaN multi-quantum well which emits ultraviolet light (approximately 400 nm). By using an underlayer having a thickness of 50 nm and doped with Si at a concentration of 2×1018/cm3, GaN grown at 1,000° C. using hydrogen, GaN grown at 780° C. using nitrogen, and In0.04Ga0.96N grown at 780° C. using nitrogen were prepared.
In Japanese Unexamined Patent Application Publication No. 2007-80996 (paragraphs 0008 to 0010, and 0015) (hereinafter referred to as “Patent Document 7) titled “GaN-based semiconductor light-emitting element and method for manufacturing the same”, the following has been disclosed.
An object Patent Document 7 is to provide a GaN-based semiconductor light-emitting element and a method for manufacturing the same, the GaN-based semiconductor light-emitting element being capable of achieving a high light-emission efficiency during operation at a high operation current density and, at the same time, of realizing a significant decrease in operation voltage.
A GaN-based semiconductor light-emitting element of a first embodiment of the Patent Document 7 has (A) a first GaN-based compound semiconductor layer having an n-type conductivity, (B) an active layer, and (C) a second GaN-based compound semiconductor layer having a p-type conductivity, and further has (D) an underlayer of a GaN-based compound semiconductor formed between the first GaN compound semiconductor layer and the active layer, and (E) a superlattice structure layer which is formed of a GaN-based semiconductor, which is provided between the active layer and the second GaN-based compound semiconductor layer, and which contains a p-type dopant.
A GaN-based semiconductor light-emitting element of a second embodiment of the Patent Document 7 in order to achieve the above object has (A) a first GaN-based compound semiconductor layer having an n-type conductivity, (B) an active layer, and (C) a second GaN-based compound semiconductor layer having a p-type conductivity, and further has (D) an underlayer of a GaN-based compound semiconductor formed between the first GaN-based compound semiconductor layer and the active layer, and the second GaN-based compound semiconductor layer has a superlattice structure.
In the GaN-based semiconductor light-emitting element of the first or the second embodiment of the Patent Document 7 including the preferable structure and configuration described above, the underlayer may be provided directly in contact with the active layer, or the structure may be formed in which a lower spacer layer of an undoped GaN-based compound semiconductor is formed between the active layer and the underlayer, and the lower spacer layer has a thickness of 50 nm or less and preferably 20 nm or less. In addition, the thickness of the underlayer is 20 nm or more and preferably 50 nm or more. In addition, as the upper limit of the thickness of the underlayer, a thickness of 1 μm may be mentioned by way of example. Furthermore, it is preferable that the underlayer and the active layer include In, and the In composition of the underlayer be 0.005 or more and be lower than that of the active layer. In addition, it is preferable that the underlayer contain an n-dopant (such as Si), and the concentration of the n-type dopant be in the range of 1×1016 to 1×1021/cm3, and more preferably in the range of 2×1017 to 2×1019/cm3. The underlayer may be basically formed of a single composition or may have a composition which gradually changes. In addition, the underlayer is preferably transparent to light-emission wavelengths.